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    KVM: arm64/sve: Add SVE support to register access ioctl interface · e1c9c983
    Dave Martin 提交于
    This patch adds the following registers for access via the
    KVM_{GET,SET}_ONE_REG interface:
    
     * KVM_REG_ARM64_SVE_ZREG(n, i) (n = 0..31) (in 2048-bit slices)
     * KVM_REG_ARM64_SVE_PREG(n, i) (n = 0..15) (in 256-bit slices)
     * KVM_REG_ARM64_SVE_FFR(i) (in 256-bit slices)
    
    In order to adapt gracefully to future architectural extensions,
    the registers are logically divided up into slices as noted above:
    the i parameter denotes the slice index.
    
    This allows us to reserve space in the ABI for future expansion of
    these registers.  However, as of today the architecture does not
    permit registers to be larger than a single slice, so no code is
    needed in the kernel to expose additional slices, for now.  The
    code can be extended later as needed to expose them up to a maximum
    of 32 slices (as carved out in the architecture itself) if they
    really exist someday.
    
    The registers are only visible for vcpus that have SVE enabled.
    They are not enumerated by KVM_GET_REG_LIST on vcpus that do not
    have SVE.
    
    Accesses to the FPSIMD registers via KVM_REG_ARM_CORE is not
    allowed for SVE-enabled vcpus: SVE-aware userspace can use the
    KVM_REG_ARM64_SVE_ZREG() interface instead to access the same
    register state.  This avoids some complex and pointless emulation
    in the kernel to convert between the two views of these aliased
    registers.
    Signed-off-by: NDave Martin <Dave.Martin@arm.com>
    Reviewed-by: NJulien Thierry <julien.thierry@arm.com>
    Tested-by: Nzhang.lei <zhang.lei@jp.fujitsu.com>
    Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
    e1c9c983
guest.c 17.3 KB