• V
    drm/i915: Implement PHY lane power gating for CHV · e0fce78f
    Ville Syrjälä 提交于
    Powergate the PHY lanes when they're not needed. For HDMI all four lanes
    are needed always, but for DP we can enable only the needed lanes. To
    power down the unused lanes we use some power down override bits in the
    DISPLAY_PHY_CONTROL register. Without the overrides it appears that the
    hardware always powers on all the lanes. When the port is disabled the
    power down override is not needed and the lanes will shut off on their
    own. That also means the override is critical to actually be able to
    access the DPIO registers before the port is actually enabled.
    
    Additionally the common lanes will power down when not needed. CL1
    remains on as long as anything else is on, CL2 will shut down when
    all the lanes in the same channel will shut down. There is one exception
    for CL2 that will be dealt in a separate patch for clarity.
    
    With potentially some lanes powered down, the DP code now has to check
    the number of active lanes before accessing PCS/TX registers. All
    registers in powered down blocks will reads as 0xffffffff, and soe we
    would drown in warnings from vlv_dpio_read() if we allowed the code
    to access all those registers.
    
    Another important detail in the DP code is the "TX latency optimal"
    setting. Normally the second TX lane acts as some kind of reset master,
    with the other lanes as slaves. But when only a single lane is enabled,
    that single lane obviously has to be the master.
    
    A bit of extra care is needed to reconstruct the initial state of the
    DISPLAY_PHY_CONTROL register since it can't be read safely. So instead
    read the actual lane status from the DPLL/PHY_STATUS registers and
    use that to determine which lanes ought to be powergated initially.
    
    We also need to switch the PHY power modes to "deep PSR" to avoid
    a hard system hang when powering down the single channel PHY.
    
    Also sprinkle a few debug prints around so that we can monitor the
    DISPLAY_PHY_STATUS changes without having to read it and risk
    corrupting it.
    
    v2: Add locking to chv_powergate_phy_lanes()
    v3: Actually enable dynamic powerdown in the PHY and deal with the
        fallout
    Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: NDeepak S <deepak.s@linux.intel.com>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    e0fce78f
intel_dp.c 173.4 KB