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    drm/i915: Try harder to disable trickle feed on VLV · e0d8d59b
    Ville Syrjälä 提交于
    The specs are a bit unclear whether the per-plane trickle feed disable
    control exists on VLV. There is another trickle feed disable control
    in the MI_ARB register.
    
    After some experimentation it turns out both the DSPCNTR trickle feed
    bits and the MI_ARB bit can be toggled. However the DSPCNTR bits don't
    seem to have any effect.
    
    The MI_ARB bit, on the other hand, has a noticable effect. I performed
    an experiment where I reduced the FIFO size via DSPARB and observed the
    effect of the MI_ARB trickle feed bit on the display.
    
    Using a 1920x1080-60 mode, with MI_ARB=0x4 the display started to have
    problems with DSPARB=0x42424242, whereas with MI_ARB=0x0 the problems
    didn't start until DSPARB=0x09090909. This seems to confirm that the
    MI_ARB trickle feed bit actually does work.
    
    So replace the use of the DSPCNTR trickle feed bits with MI_ARB
    on VLV.
    
    v2: Amend commit message with results from experimentation
    Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    e0d8d59b
intel_pm.c 154.8 KB