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    ARC: clk: introduce HSDK pll driver · daeeb438
    Eugeniy Paltsev 提交于
    HSDK board manages its clocks using various PLLs. These PLL have same
    dividers and corresponding control registers mapped to different addresses.
    So we add one common driver for such PLLs.
    
    Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
    ODIV. Output clock value is managed using these dividers.
    
    We add pre-defined tables with supported rate values and appropriate
    configurations of IDIV, FBDIV and ODIV for each value.
    
    As of today we add support for PLLs that generate clock for the
    HSDK arc cpus, system, ddr, AXI tunnel and hdmi.
    
    By this patch we add support for several plls (arc cpus pll and others),
    so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
    and regular probing for others plls.
    Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
    Reviewed-by: NVineet Gupta <vgupta@synopsys.com>
    Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
    daeeb438
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