value based on STA  target aligned to FCLK for SS corners with 10% margin

also
- group all latency together
- group all voltage state related together
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NEric Yang <eric.yang2@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>