A hardware quirk in P320h/P420m interfere with PCIe transactions on some
AMD chipsets, making P320h/P420m unusable. This workaround is to disable
ERO and NoSnoop bits in the parent and root complex for normal
functioning of these devices

NOTE: This workaround is specific to AMD chipset with a PCIe upstream
device with device id 0x5aXX
Signed-off-by: NAsai Thambi S P <asamymuthupa@micron.com>
Signed-off-by: NSam Bradshaw <sbradshaw@micron.com>
Cc: stable@kernel.org
Signed-off-by: NJens Axboe <axboe@fb.com>