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    KVM: SVM: Add MSR-based feature support for serializing LFENCE · d1d93fa9
    Tom Lendacky 提交于
    In order to determine if LFENCE is a serializing instruction on AMD
    processors, MSR 0xc0011029 (MSR_F10H_DECFG) must be read and the state
    of bit 1 checked.  This patch will add support to allow a guest to
    properly make this determination.
    
    Add the MSR feature callback operation to svm.c and add MSR 0xc0011029
    to the list of MSR-based features.  If LFENCE is serializing, then the
    feature is supported, allowing the hypervisor to set the value of the
    MSR that guest will see.  Support is also added to write (hypervisor only)
    and read the MSR value for the guest.  A write by the guest will result in
    a #GP.  A read by the guest will return the value as set by the host.  In
    this way, the support to expose the feature to the guest is controlled by
    the hypervisor.
    Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
    Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
    d1d93fa9
x86.c 234.0 KB