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    sw64: rewrite tlb flushing interfaces · d0991acd
    He Sheng 提交于
    Sunway inclusion
    category: feature
    bugzilla: https://gitee.com/openeuler/kernel/issues/I56OLG
    
    --------------------------------
    
    This patch borrows some loogarch code, ie. it rewrites following
    interfaces: flush_tlb_all(), flush_tlb_mm(), flush_tlb_page(),
    flush_tlb_range() and flush_tlb_kernel_range(), then remove
    flush_tlb() which can be achieved by flush_tlb_mm() according to
    Documentation/core-api/cachetlb.rst. To support new implementation,
    it fixes hmcall tbisasid to invalidate TLB of addr with specified
    ASID and current VPN, and adds hmcall wrasid to force update ASID.
    
    Besides, this patch adds helper cpu_asid() and asid_valid(), then
    simplify __get_new_mm_context() and its callers. That makes code
    cleaner.
    Signed-off-by: NHe Sheng <hesheng@wxiat.com>
    Reviewed-by: NCui Wei <cuiwei@wxiat.com>
    Signed-off-by: NGu Zitao <guzitao@wxiat.com>
    d0991acd
mmu_context.h 3.3 KB