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    drm/i915: Increase render/media power gating hysteresis for gen9+ · c1beabcf
    Chris Wilson 提交于
    On gen9+, after an idle period the HW will disable the entire power well
    to conserve power (by preventing current leakage). It takes around a 100
    microseconds to bring the power well back online afterwards. With the
    current hysteresis value of 25us (really 25 * 1280ns), we do not have
    sufficient time to respond to an interrupt and schedule the next execution
    before the HW powers itself down. (At present, we prevent this by
    grabbing the forcewake for prolonged periods of time, but that overkill
    fixed in the next patch.) The minimum we want to set the power gating
    hysteresis to is the length of time it takes us to service the GPU, which
    across a broad spectrum of machines is about 250us.
    
    (Note this also brings guc latency into the same ballpark as execlists.)
    
    v2: Include some notes on where I plucked the numbers from.
    
    Testcase: igt/gem_exec_nop/sequential
    Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
    Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
    Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
    Cc: Michel Thierry <michel.thierry@intel.com>
    Cc: Michal Winiarski <michal.winiarski@intel.com>
    Reviewed-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180122135541.32222-1-chris@chris-wilson.co.uk
    c1beabcf
intel_pm.c 267.4 KB