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由 KarimAllah Ahmed 提交于
Per PCIe r4.0, sec 9.3.4.1.11, the BAR registers in VF config space are all RO Zero, so skip sizing them. This is an optimization when enabling SR-IOV on a device with many VFs. Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NKarimAllah Ahmed <karahmed@amazon.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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