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    amd64_edac: correct sys address to chip select mapping · bdc30a0c
    Borislav Petkov 提交于
    The routine does the reverse mapping of the error address of a CECC back
    to the node id, DRAM controller and chip select of the DIMM which caused
    the error. We should lookup the channel using the syndromes _only_ when
    the DCTs are ganged so fix that.
    
    Also, add an early exit when there's an error while scanning for the
    csrow thus decreasing indentation levels for better readability.
    
    Finally, fixup comments.
    Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
    bdc30a0c
amd64_edac.c 84.4 KB