• V
    drm/i915/bxt: Port PLL programming BUN · b6dc71f3
    Vandana Kannan 提交于
    BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
    VCO frequencies. Program i_lockthresh in PORT_PLL_9.
    
    VCO calculated based on the formula:
    Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
    Fast Clock = Desired Output / 2
    VCO = Fast Clock * P1 * P2
    
    Prop_coeff, int_coeff, and tdctargetcnt modified according to above
    calculation.
    
    BUN 2: Port PLLs require additional programming at certain frequencies -
    DCO amplitude in PORT_PLL_10
    
    Review comments from Siva which were addressed in the initial version of the
    patch.
    	- Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
    	- Calculate for HDMI
    	- Correct values for vco = 5.4
    	- return in case of invalid vco range
    
    v2: Imre's review comments addressed
    	- change dcoampovr_en to dcoampovr_en_h
    	- change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
    	- Correct lane stagger value for 324MHz
    	- Make coef common for HDMI and DP
    	- remove superfluous comments
    
    v3: Imre's comments addressed
    	- Remove Prop_coeff, int_coeff, tdctargetcnt, dcoampovr_en, gain_ctl,
    	dcoampovr_en_h from bxt_clk_div and make them local variables.
    Signed-off-by: NVandana Kannan <vandana.kannan@intel.com>
    Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> [v1]
    Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
    Reviewed-by: NImre Deak <imre.deak@intel.com>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    b6dc71f3
i915_drv.h 100.9 KB