There are a few windows during AER/EEH when we can access PCIe I/O mapped
registers. This will harden the access to insure we do not allow PCIe
access during errors
Signed-off-by: NDave Carroll <david.carroll@microsemi.com>
Reviewed-by: NSagar Biradar <sagar.biradar@microchip.com>
Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>