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    irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling · 96806229
    Marc Zyngier 提交于
    When a vPE is made resident, the GIC starts parsing the virtual pending
    table to deliver pending interrupts. This takes place asynchronously,
    and can at times take a long while. Long enough that the vcpu enters
    the guest and hits WFI before any interrupt has been signaled yet.
    The vcpu then exits, blocks, and now gets a doorbell. Rince, repeat.
    
    In order to avoid the above, a (optional on GICv4, mandatory on v4.1)
    feature allows the GIC to feedback to the hypervisor whether it is
    done parsing the VPT by clearing the GICR_VPENDBASER.Dirty bit.
    The hypervisor can then wait until the GIC is ready before actually
    running the vPE.
    
    Plug the detection code as well as polling on vPE schedule. While
    at it, tidy-up the kernel message that displays the GICv4 optional
    features.
    Reviewed-by: NZenghui Yu <yuzenghui@huawei.com>
    Signed-off-by: NMarc Zyngier <maz@kernel.org>
    96806229
irq-gic-v3.c 53.0 KB