There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.
Signed-off-by: NRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: NAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220217082626.15728-2-rex-bc.chen@mediatek.comSigned-off-by: NMatthias Brugger <matthias.bgg@gmail.com>