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    ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR · b46c0f74
    Stephen Boyd 提交于
    armv7's flush_cache_all() flushes caches via set/way. To
    determine the cache attributes (line size, number of sets,
    etc.) the assembly first writes the CSSELR register to select a
    cache level and then reads the CCSIDR register. The CSSELR register
    is banked per-cpu and is used to determine which cache level CCSIDR
    reads. If the task is migrated between when the CSSELR is written and
    the CCSIDR is read the CCSIDR value may be for an unexpected cache
    level (for example L1 instead of L2) and incorrect cache flushing
    could occur.
    
    Disable interrupts across the write and read so that the correct
    cache attributes are read and used for the cache flushing
    routine. We disable interrupts instead of disabling preemption
    because the critical section is only 3 instructions and we want
    to call v7_dcache_flush_all from __v7_setup which doesn't have a
    full kernel stack with a struct thread_info.
    
    This fixes a problem we see in scm_call() when flush_cache_all()
    is called from preemptible context and sometimes the L2 cache is
    not properly flushed out.
    Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
    Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
    Reviewed-by: NNicolas Pitre <nico@linaro.org>
    Cc: stable@vger.kernel.org
    Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
    b46c0f74
cache-v7.S 8.8 KB