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    irqchip: mips-gic: Clean up mti, reserved-cpu-vectors handling · b2b2e584
    Paul Burton 提交于
    When parsing mti,reserved-cpu-vectors we generate a mask of all bits
    that have been declared reserved, the loop through starting from bit 2
    to find one that isn't reserved (ie. is zero).
    
    This patch accomplishes the same task more simply by:
    
      - Inititialising the reserved mask to 0x3 (ie. the 2 software
        interrupts). This means we don't need to skip them later as the loop
        previously has.
    
      - Replacing the loop checking for zero bits with find_first_zero_bit,
        which fits our needs now that the 2 software interrupts are marked
        reserved. This requires that the type of reserved is changed to
        unsigned long so that it's suitable for use with bitmap functions.
    
      - Replacing the magic number 8 with the hamming weight of the ST0_IM
        field - ie. the number of bits that a MIPS CPU has for interrupt
        inputs. This is still a compile-time constant 8, but makes it
        clearer why it's 8.
    Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
    Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
    Cc: Jason Cooper <jason@lakedaemon.net>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/17054/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    b2b2e584
irq-mips-gic.c 19.5 KB