Add hwmod entries for the PWMSS on DRA7.

Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
Signed-off-by: NVignesh R <vigneshr@ti.com>
[fcooper@ti.com: Do not add eQEP, ePWM and eCAP hwmod entries]
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
[paul@pwsan.com: fixed sparse warnings; added missing comments]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>