This layer is responsible for
- Enumerating over PCI bus
- Inform FW about host readiness
- Provide HW interface to transport layer for control and messages
- Interrupt handling and routing

Original-author: Daniel Drubin <daniel.drubin@intel.com>
Reviewed-and-tested-by: NOoi, Joyce <joyce.ooi@intel.com>
Tested-by: NGrant Likely <grant.likely@secretlab.ca>
Tested-by: NRann Bar-On <rb6@duke.edu>
Tested-by: NAtri Bhattacharya <badshah400@aim.com>
Signed-off-by: NSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>