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    x86/cpufeatures: Enumerate MOVDIR64B instruction · ace6485a
    Fenghua Yu 提交于
    MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
    Direct store is implemented by using write combining (WC) for writing
    data directly into memory without caching the data.
    
    In low latency offload (e.g. Non-Volatile Memory, etc), MOVDIR64B writes
    work descriptors (and data in some cases) to device-hosted work-queues
    atomically without cache pollution.
    
    Availability of the MOVDIR64B instruction is indicated by the
    presence of the CPUID feature flag MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]).
    
    Please check the latest Intel Architecture Instruction Set Extensions
    and Future Features Programming Reference for more details on the CPUID
    feature MOVDIR64B flag.
    Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
    Cc: Andy Lutomirski <luto@amacapital.net>
    Cc: Ashok Raj <ashok.raj@intel.com>
    Cc: Borislav Petkov <bp@alien8.de>
    Cc: Brian Gerst <brgerst@gmail.com>
    Cc: Denys Vlasenko <dvlasenk@redhat.com>
    Cc: H. Peter Anvin <hpa@zytor.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Ravi V Shankar <ravi.v.shankar@intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Link: http://lkml.kernel.org/r/1540418237-125817-3-git-send-email-fenghua.yu@intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
    ace6485a
cpufeatures.h 23.6 KB