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    drm/i915/bdw: Implement interrupt changes · abd58f01
    Ben Widawsky 提交于
    The interrupt handling implementation remains the same as previous
    generations with the 4 types of registers, status, identity, mask, and
    enable. However the layout of where the bits go have changed entirely.
    To address these changes, all of the interrupt vfuncs needed special
    gen8 code.
    
    The way it works is there is a top level status register now which
    informs the interrupt service routine which unit caused the interrupt,
    and therefore which interrupt registers to read to process the
    interrupt. For display the division is quite logical, a set of interrupt
    registers for each pipe, and in addition to those, a set each for "misc"
    and port.
    
    For GT the things get a bit hairy, as seen by the code. Each of the GT
    units has it's own bits defined. They all look *very similar* and
    resides in 16 bits of a GT register. As an example, RCS and BCS share
    register 0. To compact the code a bit, at a slight expense to
    complexity, this is exactly how the code works as well. 2 structures are
    added to the ring buffer so that our ring buffer interrupt handling code
    knows which ring shares the interrupt registers, and a shift value (ie.
    the top or bottom 16 bits of the register).
    
    The above allows us to kept the interrupt register caching scheme, the
    per interrupt enables, and the code to mask and unmask interrupts
    relatively clean (again at the cost of some more complexity).
    
    Most of the GT units mentioned above are command streamers, and so the
    symmetry should work quite well for even the yet to be implemented rings
    which Broadwell adds.
    
    v2: Fixes up a couple of bugs, and is more verbose about errors in the
    Broadwell interrupt handler.
    
    v3: fix DE_MISC IER offset
    
    v4: Simplify interrupts:
    I totally misread the docs the first time I implemented interrupts, and
    so this should greatly simplify the mess. Unlike GEN6, we never touch
    the regular mask registers in irq_get/put.
    
    v5: Rebased on to of recent pch hotplug setup changes.
    
    v6: Fixup on top of moving num_pipes to intel_info.
    
    v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
    wired up ibx_hpd_irq_setup for gen8.
    
    v8: Rebase on top of Jani's asle handling rework.
    
    v9: Rebase on top of Ben's VECS enabling for Haswell, where he
    unfortunately went OCD on the gt irq #defines. Not that they're still
    not yet fully consistent:
    - Used the GT_RENDER_ #defines + bdw shifts.
    - Dropped the shift from the L3_PARITY stuff, seemed clearer.
    - s/irq_refcount/irq_refcount.gt/
    
    v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
    refactoring from Zhao Yakui <yakui.zhao@intel.com>
    
    v11: Rebase on top of the interrupt cleanups in upstream.
    
    v12: Rebase on top of Ben's DPF changes in upstream.
    
    v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
    exactly needs to be done. Requested by Ben.
    
    v14: Fix the patch.
    - Drop the mask of reserved bits and assorted logic, it doesn't match
      the spec.
    - Do the posting read inconditionally instead of commenting it out.
    - Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
    - Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
      we actually will need to use them.
    - Enclose macros in do {} while (0) (checkpatch).
    - Clear DE_MISC interrupt bits only after having processed them.
    - Fix whitespace fail (checkpatch).
    - Fix overtly long lines where appropriate (checkpatch).
    - Don't use typedef'ed private_t (maintainer-scripts).
    - Align the function parameter list correctly.
    
    Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    
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    abd58f01
i915_drv.h 75.6 KB