stable inclusion
from stable-5.10.4
commit 9e737d120b524b7bb3937af282eb452276830902
bugzilla: 46903

--------------------------------

[ Upstream commit 5047ab95 ]

PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: NRob Clark <robdclark@chromium.org>
Signed-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>