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    nvme: set controller enable bit in a separate write · aa41d2fe
    Niklas Cassel 提交于
    The NVM Express Base Specification 2.0 specifies in the description
    of the CC – Controller Configuration register:
    "Host software shall set the Arbitration Mechanism Selected (CC.AMS),
    the Memory Page Size (CC.MPS), and the I/O Command Set Selected (CC.CSS)
    to valid values prior to enabling the controller by setting CC.EN to ‘1’.
    
    While we haven't seen any controller misbehaving while setting all bits
    in a single write, let's do it in the order that it is written in the
    spec, as there could potentially be controllers that are implemented to
    rely on the configuration bits being set before enabling the controller.
    Signed-off-by: NNiklas Cassel <niklas.cassel@wdc.com>
    Signed-off-by: NChristoph Hellwig <hch@lst.de>
    aa41d2fe
core.c 130.2 KB