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    iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S · 9cff86fd
    Yisheng Xie 提交于
    According to Spec, it is ILLEGAL to set STE.S1STALLD if STALL_MODEL
    is not 0b00, which means we should not disable stall mode if stall
    or terminate mode is not configuable.
    
    Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which
    means if stall mode is force we should always set CD.S.
    
    As Jean-Philippe's suggestion, this patch introduce a feature bit
    ARM_SMMU_FEAT_STALL_FORCE, which means smmu only supports stall force.
    Therefore, we can avoid the ILLEGAL setting of STE.S1STALLD.by checking
    ARM_SMMU_FEAT_STALL_FORCE.
    
    This patch keeps the ARM_SMMU_FEAT_STALLS as the meaning of stall supported
    (force or configuable) to easy to expand the future function, i.e. we can
    only use ARM_SMMU_FEAT_STALLS to check whether we should register fault
    handle or enable master can_stall, etc to supporte platform SVM.
    
    The feature bit, STE.S1STALLD and CD.S setting will be like:
    
    STALL_MODEL  FEATURE                                         S1STALLD CD.S
    0b00         ARM_SMMU_FEAT_STALLS                                 0b1 0b0
    0b01         !ARM_SMMU_FEAT_STALLS && !ARM_SMMU_FEAT_STALL_FORCE  0b0 0b0
    0b10         ARM_SMMU_FEAT_STALLS && ARM_SMMU_FEAT_STALL_FORCE    0b0 0b1
    
    after apply this patch.
    Signed-off-by: NYisheng Xie <xieyisheng1@huawei.com>
    Signed-off-by: NWill Deacon <will.deacon@arm.com>
    9cff86fd
arm-smmu-v3.c 74.2 KB