[Why]
DIG_FIFO_OUTPUT_PIXEL_MODE not being set for dcn314
resulting in incorrect timing for YCbCr4:2:0

[How]
Copy the implementation of set_pixels_per_cycle from dcn32
over to dcn314
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NDaniel Miess <Daniel.Miess@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>