SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: NVincent Wan <vincent.wan@amd.com>
Signed-off-by: NWan Zongshun <mcuos.com@gmail.com>
Signed-off-by: NArindam Nath <arindam.nath@amd.com>
Tested-by: NVikram B <vikram.b@amd.com>
Tested-by: NRaghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>