The final version of fusb300 controller adds EPSET0_STL_CLR
for clearing EP0 stall and also removes EPSET0_EPn_TX0BYTE.

fusb300_udc driver is tested on FARADAY platform a369 with
FUSB300 FPGA v1.8
Signed-off-by: NYuan-Hsin Chen <yhchen@faraday-tech.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>