• G
    csky: fixup CACHEV1 store instruction fast retire · 96354ad7
    Guo Ren 提交于
    For I/O access, 810/807 store instruction fast retire will cause wrong
    primitive. For example:
    
    	stw (clear interrupt source)
    	stw (unmask interrupt controller)
    	enable interrupt
    
    stw is fast retire instruction. When PC is run at enable interrupt
    stage, the clear interrupt source hasn't finished. It will cause another
    wrong irq-enter.
    
    So use mb() to prevent above.
    Signed-off-by: NGuo Ren <ren_guo@c-sky.com>
    Cc: Lu Baoquan <lu.baoquan@intellif.com>
    96354ad7
io.h 1.6 KB