ARMv7 counters other than the CPU cycle counter only work if the Secure
Debug Enable Register (SDER) SUNIDEN bit is set.

Since access to the SDER is only possible in secure state, it will
only be done if the device tree property "secure-reg-access" is set.

Without this:

 Performance counter stats for 'sleep 1':

          14606094 cycles                    #    0.000 GHz
                 0 instructions              #    0.00  insns per cycle

After applying:

 Performance counter stats for 'sleep 1':

           5843809 cycles
           2566484 instructions              #    0.44  insns per cycle

       1.020144000 seconds time elapsed

Some platforms (eg i.MX53) may also need additional platform specific
setup.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: NPooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: NGeorge G. Davis <george_davis@mentor.com>
[will: add warning if property is found on arm64]
Signed-off-by: NWill Deacon <will.deacon@arm.com>