• J
    scsi: lpfc: Revise interrupt coalescing for missing scenarios · 8156d378
    James Smart 提交于
    The existing "auto eq delay" mechanism was sometimes skipping over an EQ,
    not ramping the coalescing down under light load fast enough, and in other
    cases never kicked in as cpu sharing by multiple vectors didn't quite add
    up right.
    
    Tweak the interrupt mechanism such that:
    
     - Add a flag to the EQ to force checking for colaescing values when being
       serviced in the interrupt handler.  The flag will be set by any CQ bound
       to the EQ whenever the number of CQ elements process in a single scan
       meets or exceeds the hardware queue notify level. E.g. there's a
       significant number of completions happening.
    
     - In the heartbeat work item that checks coalescing:
    
       - Replace the structure that was counting the number of EQs that
         interrupted on a single cpu with a new structure that looks at the EQ
         to see whether EQ currently has a coalescing value (thus it should be
         re-evaluate) or was marked by the new flag indicating heavy
         completions.
    
       - When a cpu, which may be servicing multiple vectors, had at least 1 EQ
         that should be checked, a new coalescing delay is calculated based on
         the number of interrupts that occurred on the cpu.
    
       - The new coalescing value is then applied to the EQs that had
         interrupted on the cpu.
    
    Link: https://lore.kernel.org/r/20191018211832.7917-11-jsmart2021@gmail.comSigned-off-by: NDick Kennedy <dick.kennedy@broadcom.com>
    Signed-off-by: NJames Smart <jsmart2021@gmail.com>
    Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
    8156d378
lpfc_hw4.h 166.9 KB