• K
    PCI: Add Downstream Port Containment driver · 26e51571
    Keith Busch 提交于
    Add driver for the PCI Express Downstream Port Containment extended
    capability.  DPC is an optional capability to contain uncorrectable errors
    below a port.
    
    For more information on DPC, please see PCI Express Base Specification
    Revision 4, section 7.31, or view the PCI-SIG DPC ECN here:
    
      https://pcisig.com/sites/default/files/specification_documents/ECN_DPC_2012-02-09_finalized.pdf
    
    When a DPC event is triggered, the hardware disables downstream links, so
    the DPC driver schedules removal for all devices below this port.  This may
    happen concurrently with a PCIe hotplug driver if enabled.  When all
    downstream devices are removed and the link state transitions to disabled,
    the DPC driver clears the DPC status and interrupt bits so the link may
    retrain for a newly connected device.
    
    [bhelgaas: clear (not set) DPC_CTL bits on remove, whitespace cleanup]
    Signed-off-by: NKeith Busch <keith.busch@intel.com>
    Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
    Cc: Lukas Wunner <lukas@wunner.de>
    26e51571
pcie-dpc.c 4.5 KB