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    RDMA/cxgb3: Fixes for zero STag · 4ab928f6
    Steve Wise 提交于
    Handling the zero STag in receive work request requires some extra
    logic in the driver:
    
     - Only set the QP_PRIV bit for kernel mode QPs.
    
    - Add a zero STag build function for recv wrs. The uP needs a PBL
      allocated and passed down in the recv WR so it can construct a HW
      PBL for the zero STag S/G entries.  Note: we need to place a few
      restrictions on zero STag usage because of this:
    
      1) all SGEs in a recv WR must either be zero STag or not.  No mixing.
    
      2) an individual SGE length cannot exceed 128MB for a zero-stag SGE.
         This should be OK since it's not really practical to allocate
         such a large chunk of pinned contiguous DMA mapped memory.
    
    - Add an optimized non-zero-STag recv wr format for kernel users.
      This is needed to optimize both zero and non-zero STag cracking in
      the recv path for kernel users.
    
     - Remove the iwch_ prefix from the static build functions.
    
     - Bump required FW version.
    Signed-off-by: NSteve Wise <swise@opengridcomputing.com>
    4ab928f6
iwch_qp.c 31.9 KB