Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.

But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.
Signed-off-by: NXing Zheng <zhengxing@rock-chips.com>
Reviewed-by: NStephen Barber <smbarber@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>