RAS error address translation algorithm is common
across dGPU and A + A platform as along as the SOC
integrates the same generation of UMC IP.

UMC RAS is managed by x86 MCA on A + A platform,
umc_ras in GPU driver is not initialized at all on
A + A platform. In such case, any umc_ras callback
implemented for dGPU config shouldn't be invoked
from A + A specific callback.

The change moves convert_error_address out of dGPU
umc_ras structure and makes it share between A + A
and dGPU config.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NStanley Yang <Stanley.Yang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>