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    arm64: implement CPPC FFH support using AMUs · 68c5debc
    Ionela Voinescu 提交于
    If Activity Monitors (AMUs) are present, two of the counters can be used
    to implement support for CPPC's (Collaborative Processor Performance
    Control) delivered and reference performance monitoring functionality
    using FFH (Functional Fixed Hardware).
    
    Given that counters for a certain CPU can only be read from that CPU,
    while FFH operations can be called from any CPU for any of the CPUs, use
    smp_call_function_single() to provide the requested values.
    
    Therefore, depending on the register addresses, the following values
    are returned:
     - 0x0 (DeliveredPerformanceCounterRegister): AMU core counter
     - 0x1 (ReferencePerformanceCounterRegister): AMU constant counter
    
    The use of Activity Monitors is hidden behind the generic
    cpu_read_{corecnt,constcnt}() functions.
    
    Read functionality for these two registers represents the only current
    FFH support for CPPC. Read operations for other register values or write
    operation for all registers are unsupported. Therefore, keep CPPC's FFH
    unsupported if no CPUs have valid AMU frequency counters. For this
    purpose, the get_cpu_with_amu_feat() is introduced.
    Signed-off-by: NIonela Voinescu <ionela.voinescu@arm.com>
    Reviewed-by: NSudeep Holla <sudeep.holla@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Link: https://lore.kernel.org/r/20201106125334.21570-4-ionela.voinescu@arm.comSigned-off-by: NCatalin Marinas <catalin.marinas@arm.com>
    68c5debc
cpufeature.h 25.4 KB