Sunway inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I56OLG

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SW64 architecture manuals say that icache of C3A/C3B is VIVT with
ICtag which is mapped to physical memory. That means icache doesn't
need to be flushed when instruction pages change.
Signed-off-by: NHe Sheng <hesheng@wxiat.com>
Signed-off-by: NGu Zitao <guzitao@wxiat.com>