Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are
present on the K3 J721E SoCs. The two ICSSGs are identical to each other
for the most part, with the ICSSG1 supporting slightly enhanced features
for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by
a PRUSS subsystem node and other child nodes. These nodes are enabled by
default.

The ICSSGs on K3 J721E SoCs are revised versions of the ICSSG on the first
AM65x SR1.0 SoCs. The PRU IRAMs are slightly smaller, and the IP includes
two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB of IRAMs
and leverage the same host interrupts as the regular PRU cores. All The
ICSSG host interrupts intended towards the main Arm core are also shared
with other processors on the SoC, and can be partitioned as per system
integration needs.

The ICSSG subsystem node contains the entire address space. The various
sub-modules of the ICSSG are represented as individual child nodes (so
platform devices themselves) of the PRUSS subsystem node. These include
the two PRU cores, two RTU cores, two Tx_PRU cores and the interrupt
controller. All the Data RAMs are represented within a child node of
its own named 'memories' without any compatible. The Real Time Media
Independent Interface controller (MII_RT), the Gigabit capable MII_G_RT
and the CFG sub-module are represented as syscon nodes. The ICSSG CFG
sub-module provides two internal clock muxes, and these are represented
as children of the CFG child node 'clocks' by the 'coreclk-mux' and
iepclk-mux' clk nodes. The default parents for these mux clocks are also
defined using the assigned-clock-parents property.

The DT nodes use all standard properties. The regs property in the
PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the
Debug and Control sub-modules for that PRU core. The firmware for each
PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property.

The default names for the firmware images for each PRU, RTU and Tx_PRU
cores are defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
 ICSSG0 PRU0 Core    : j7-pru0_0-fw   ; PRU1 Core    : j7-pru0_1-fw
 ICSSG0 RTU0 Core    : j7-rtu0_0-fw   ; RTU1 Core    : j7-rtu0_1-fw
 ICSSG0 Tx_PRU0 Core : j7-txpru0_0-fw ; Tx_PRU1 Core : j7-txpru0_1-fw
 ICSSG1 PRU0 Core    : j7-pru1_0-fw   ; PRU1 Core    : j7-pru1_1-fw
 ICSSG1 RTU0 Core    : j7-rtu1_0-fw   ; RTU1 Core    : j7-rtu1_1-fw
 ICSSG1 Tx_PRU0 Core : j7-txpru1_0-fw ; Tx_PRU1 Core : j7-txpru1_1-fw

Note:
1. The ICSSG INTC on J721E SoCs share all the host interrupts with other
   processors, so use the 'ti,irqs-reserved' property in derivative board
   dts files _if_ any of them should not be handled by the host OS.
2. There are few more sub-modules like the Industrial Ethernet Peripherals
   (IEPs), MDIO, PWM, UART that do not have bindings and so will be added
   in the future.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210304160712.8452-3-s-anna@ti.com