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由 Yu Zhao 提交于
mainline inclusion from mainline-v6.1-rc1 commit eed9a328 category: feature bugzilla: https://gitee.com/openeuler/open-source-summer/issues/I55Z0L CVE: NA Reference: https://android-review.googlesource.com/c/kernel/common/+/2050907/10 ---------------------------------------------------------------------- Some architectures support the accessed bit in non-leaf PMD entries, e.g., x86 sets the accessed bit in a non-leaf PMD entry when using it as part of linear address translation [1]. Page table walkers that clear the accessed bit may use this capability to reduce their search space. Note that: 1. Although an inline function is preferable, this capability is added as a configuration option for consistency with the existing macros. 2. Due to the little interest in other varieties, this capability was only tested on Intel and AMD CPUs. [1]: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 (June 2021), section 4.8 Link: https://lore.kernel.org/r/20220309021230.721028-3-yuzhao@google.com/Signed-off-by: NYu Zhao <yuzhao@google.com> Reviewed-by: NBarry Song <baohua@kernel.org> Acked-by: NBrian Geffon <bgeffon@google.com> Acked-by: NJan Alexander Steffens (heftig) <heftig@archlinux.org> Acked-by: NOleksandr Natalenko <oleksandr@natalenko.name> Acked-by: NSteven Barrett <steven@liquorix.net> Acked-by: NSuleiman Souhlal <suleiman@google.com> Tested-by: NDaniel Byrne <djbyrne@mtu.edu> Tested-by: NDonald Carr <d@chaos-reins.com> Tested-by: NHolger Hoffstätte <holger@applied-asynchrony.com> Tested-by: NKonstantin Kharlamov <Hi-Angel@yandex.ru> Tested-by: NShuang Zhai <szhai2@cs.rochester.edu> Tested-by: NSofia Trinh <sofia.trinh@edi.works> Tested-by: NVaibhav Jain <vaibhav@linux.ibm.com> Bug: 227651406 Signed-off-by: NKalesh Singh <kaleshsingh@google.com> Change-Id: I73f84a21fd315192eaa3e6443334ed1bccb4e99e Signed-off-by: NYuLinjia <3110442349@qq.com>
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