Previously, SCR.SSIEN and SCR.TE were enabled at once if no capture
stream was also running.
This may not give a chance for the DMA to write the first sample in
TX FIFO before the streaming starts on the PCM bus, inserting void
samples first.
Those void samples are then responsible for slipping the channels.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>