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由 Bruce Allan 提交于
The Host Wakeup Active bit in the PHY Port General Configuration register (page 769 register 17) must be cleared after every PHY reset to prevent an unexpected wake signal from the PHY. Originally, this was accomplished by simply reading the PHY Wakeup Control register on page 800 which clears the Host Wakeup Active bit as a side-effect. Unfortunately, a hardware bug on the 82577 and 82578 PHY can cause unexpected behavior when registers on page 800 are accessed while in gigabit mode. This patch changes the remaining instances when the Host Wakeup Active bit needs to be cleared while possibly in gigabit mode by accessing the Port General Configuration register directly instead of accessing any register on page 800. Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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