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由 Geert Uytterhoeven 提交于
Add the CR core clock, which is used by the Secure Engine (SCEG). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Tested-by: NGilad Ben-Yossef <gilad@benyossef.com>
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