“e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f”上不存在“arch/mips/include/asm/processor.h”
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    powerpc: Optimise smp_rmb · 957ab07b
    Nick Piggin 提交于
    After commit 598056d5 ("[POWERPC] Fix
    rmb to order cacheable vs. noncacheable"), rmb() becomes a sync
    instruction, which is needed to order cacheable vs noncacheable loads.
    However smp_rmb() is #defined to rmb(), and smp_rmb() can be an
    lwsync.
    
    This restores smp_rmb() performance by using lwsync there and updates
    the comments.
    Signed-off-by: NNick Piggin <npiggin@suse.de>
    Signed-off-by: NPaul Mackerras <paulus@samba.org>
    957ab07b
system.h 14.5 KB