• G
    csky: Fix TLB maintenance synchronization problem · 3b756ccd
    Guo Ren 提交于
    TLB invalidate didn't contain a barrier operation in csky cpu and
    we need to prevent previous PTW response after TLB invalidation
    instruction. Of cause, the ASID changing also needs to take care
    of the issue.
    
    CPU0                    CPU1
    ===============         ===============
    set_pte
    sync_is()        ->     See the previous set_pte for all harts
    tlbi.vas         ->     Invalidate all harts TLB entry & flush pipeline
    Signed-off-by: NGuo Ren <guoren@linux.alibaba.com>
    3b756ccd
ckmmu.h 2.2 KB
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