Currently ACPI populates just the minimum information about the last
level cache from PPTT in order to feed the same to build sched_domains.
Similar support for DT platforms is not present.

In order to enable the same, the entire cache hierarchy information can
be built as part of CPU topoplogy parsing both on ACPI and DT platforms.

Note that this change builds the cacheinfo early even on ACPI systems,
but the current mechanism of building llc_sibling mask remains unchanged.

Link: https://lore.kernel.org/r/20220704101605.1318280-10-sudeep.holla@arm.comTested-by: NIonela Voinescu <ionela.voinescu@arm.com>
Tested-by: NConor Dooley <conor.dooley@microchip.com>
Reviewed-by: NGavin Shan <gshan@redhat.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>