The output tap delay controls helps maintain the hold requirements for
eMMC. The exact value is dependent on the SoC and other factors, though
it isn't really an exact science. But the default of 0 is not very good,
as it doesn't give the eMMC much hold time, so let's bump up to 4
(approx 90 degree phase?). If we need to configure this any further
(e.g., based on board or speed factors), we may need to consider a
device tree representation.
Suggested-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>