If there is a gap between xfer mode and command register writes,
tegra SDMMC controller can sometimes issue a spurious command before
the CMD register is written. To avoid this, these two registers need
to be written together in a single write operation.

This is implemented as an NVQUIRK as it applies to T114, T124 and
T132.
Signed-off-by: NPavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>