Change the definition of riscTx and riscRx to unsigned integer instead of
enum, and change their values to support 4 risc allocation if the qe has
4 RISC engines.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>