• M
    MIPS: Fix CP0 counter erratum detection for R4k CPUs · 3454b112
    Maciej W. Rozycki 提交于
    stable inclusion
    from stable-v5.10.115
    commit 326f02f172d08b959da035f69e93e6afdf91745c
    category: bugfix
    bugzilla: https://gitee.com/openeuler/kernel/issues/I5IZ9C
    
    Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=326f02f172d08b959da035f69e93e6afdf91745c
    
    --------------------------------
    
    commit f0a6c68f upstream.
    
    Fix the discrepancy between the two places we check for the CP0 counter
    erratum in along with the incorrect comparison of the R4400 revision
    number against 0x30 which matches none and consistently consider all
    R4000 and R4400 processors affected, as documented in processor errata
    publications[1][2][3], following the mapping between CP0 PRId register
    values and processor models:
    
      PRId   |  Processor Model
    ---------+--------------------
    00000422 | R4000 Revision 2.2
    00000430 | R4000 Revision 3.0
    00000440 | R4400 Revision 1.0
    00000450 | R4400 Revision 2.0
    00000460 | R4400 Revision 3.0
    
    No other revision of either processor has ever been spotted.
    
    Contrary to what has been stated in commit ce202cbb ("[MIPS] Assume
    R4000/R4400 newer than 3.0 don't have the mfc0 count bug") marking the
    CP0 counter as buggy does not preclude it from being used as either a
    clock event or a clock source device.  It just cannot be used as both at
    a time, because in that case clock event interrupts will be occasionally
    lost, and the use as a clock event device takes precedence.
    
    Compare against 0x4ff in `can_use_mips_counter' so that a single machine
    instruction is produced.
    
    References:
    
    [1] "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", MIPS
        Technologies Inc., May 10, 1994, Erratum 53, p.13
    
    [2] "MIPS R4400PC/SC Errata, Processor Revision 1.0", MIPS Technologies
        Inc., February 9, 1994, Erratum 21, p.4
    
    [3] "MIPS R4400PC/SC Errata, Processor Revision 2.0 & 3.0", MIPS
        Technologies Inc., January 24, 1995, Erratum 14, p.3
    Signed-off-by: NMaciej W. Rozycki <macro@orcam.me.uk>
    Fixes: ce202cbb ("[MIPS] Assume R4000/R4400 newer than 3.0 don't have the mfc0 count bug")
    Cc: stable@vger.kernel.org # v2.6.24+
    Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
    Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
    Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
    Acked-by: NXie XiuQi <xiexiuqi@huawei.com>
    3454b112
timex.h 3.0 KB