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    x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs · cabb5bd7
    Hans Rosenfeld 提交于
    L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can be used
    for evictions by the L2 cache of each compute unit. By writing a 4-bit
    hexadecimal mask into the the sysfs file
    /sys/devices/system/cpu/cpuX/cache/index3/subcaches, the user can set the
    enabled subcaches for a CPU.
    
    The settings are directly read from and written to the hardware, so there is no
    way to have contradicting settings for two CPUs belonging to the same compute
    unit. Writing will always overwrite any previous setting for a compute unit.
    Signed-off-by: NHans Rosenfeld <hans.rosenfeld@amd.com>
    Cc: <Andreas.Herrmann3@amd.com>
    LKML-Reference: <1297098639-431383-1-git-send-email-hans.rosenfeld@amd.com>
    [ -v3: minor style fixes ]
    Signed-off-by: NIngo Molnar <mingo@elte.hu>
    cabb5bd7
intel_cacheinfo.c 32.4 KB