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    drm/i915: Fix pte updates in ggtt clear range · 2ff4aeac
    Ben Widawsky 提交于
    This bug was introduced by me:
    commit e76e9aeb
    Author: Ben Widawsky <ben@bwidawsk.net>
    Date:   Sun Nov 4 09:21:27 2012 -0800
    
        drm/i915: Stop using AGP layer for GEN6+
    
    The existing code uses memset_io which follows memset semantics in only
    guaranteeing a write of individual bytes. Since a PTE entry is 4 bytes,
    this can only be correct if the scratch page address is 0.
    
    This caused unsightly errors when we clear the range at load time,
    though I'm not really sure what the heck is referencing that memory
    anyway. I caught this is because I believe we have some other bug where
    the display is doing reads of memory we feel should be cleared (or we
    are relying on scratch pages to be a specific value).
    Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
    Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    2ff4aeac
i915_gem_gtt.c 19.2 KB